The various parts of a computer, such as processors, memory elements and I/O devices, communicate with each other through busses which may comprise many signal lines. One group of signal lines in a bus, called the handshake lines, controls the timing of data transfers between the various asynchronous parts of the computer system. The handshake lines carry the signals that dictate when each data transfer begins and ends. The handshakes start and stop transactions and exert the same functional control on all transactions regardless of type.
Known protocols fall generally into three broad classes: synchronous (clocked transfer, one clock period per transfer); asynchronous (unclocked); and semisynchronous (clocked transfer, one or more clock periods per transfer).
The principal advantage of data communications in a synchronous system is simplicity. Data transfers are controlled through a single signal and the data transfers run with minimal overhead in terms of skew, setup, hold and propagation delays. However, data communication in a synchronous system has a serious problem dealing with slow devices connected to the bus. The fully synchronous bus cannot accommodate devices whose access time is greater than the time available during a bus clock period. With a fully synchronous protocol, the bus clock rate must be set slow enough to satisfy the slowest device on the bus where the device's response time includes the effect of propagation delays due to physical separation. But this reduces the maximum data rate for all transactions, and the slow device has thereby decreased the potential system performance even though the slow device may be rarely accessed.
For the computer system that comprises a mix of devices with widely varying access times, the synchronous communications protocol may be inappropriate because the bus runs at the speed of the slowest device. It is advantageous for the system to allow for fast transactions for fast devices and slow transactions for slow or distant devices, so that transaction time varies with the device rather than being fixed by a system clock. To achieve this advantage, in some systems, data transferral is performed by utilizing asynchronous devices and a fully handshaked protocol wherein the communicating elements must positively acknowledge each step of every transaction. However, this protocol is inefficient due to the multitude of signal transitions which must be monitored to complete a data transfer. Further, the delays involved in waiting for the acknowledgement of each step also slow the process.
Other known systems employ a wait signal or clock cycle stall mechanism generated by the responding element of an asynchronous system to delay the transfer for an indeterminate number of clock cycles until the responding element is ready to receive data. Since the wait signal must be asserted within a fixed period of time, the length of the bus is physically limited. Also, the clock stall mechanism involves a complex circuit.
Still other known systems employ a split-cycle protocol in which the responding unit of a read memory transaction becomes the transmitting unit of a write transaction when it has obtained the necessary data. This allows the bus to be used for other transactions during the intervening idle cycles. In this system, however, both communicating elements must have the logic necessary to assume both master and slave roles in a transaction. Further, the communicating elements must have the logic necessary for bus arbitration in order to prevent conflicts when accessing the bus to transmit data.
It would be advantageous to employ a data transfer protocol that improves the performance of communications between asynchronous system elements, and reduces the complexities of the bus interface signals.